Following our previous discussion of chip ferrite beads, in this lesson we will talk about what you need to know to make the best use of chip 3-terminal capacitors.
1. Considerations when mounting chip 3-terminal capacitors on a multilayer substrate
Chip 3-terminal capacitors have lower impedance of the ground terminal compared to normal 2-terminal capacitors, and this is the key to high-frequency noise suppression. However, taking advantage of this feature requires paying attention to the pattern design for mounting, and designing the ground-side pattern to be as thick and short as possible. Similar considerations apply when mounting on a multilayer substrate.
The examples in Figure 1 illustrate the effects on noise suppression of changes to the way the 3-terminal capacitor is mounted on a multilayer substrate, in particular the connection to the GND layer. In these examples, the GND layer is located near the opposite side of the surface where the MCU is mounted. An example of a short connection to the GND layer is illustrated in Example A, in which the 3-terminal capacitor is mounted close to the GND layer, on the opposite side of the MCU mounting surface. Example C, in which the 3-terminal capacitor is mounted on the same plane as the MCU, shows the result of a longer distance to the GND layer compared to Example A. Notice the significant difference in noise level between Examples A and C. When considering the GND pattern, it is not enough to think about planarity; one must also take into account the length of the vias. In Example B in Figure 1, the power input and output to the 3-terminal capacitor pass through the same layer, without the clear separation found in Example A. (Since this is difficult to explain in writing, please refer to the figure.) In this case the noise level is slightly higher than for Example A. This is likely because the vias of the entrance and exit to the 3-terminal capacitor are so close that some of the noise, rather than passing through the 3-terminal capacitor, is bypassing it due to capacitive coupling between the vias. As this example shows, you need to pay attention to the routing outside of the capacitor in order to get the best performance out of the 3-terminal capacitor. Figure 2 shows the key points for mounting a chip 3-terminal capacitor.
2. "Non-through" connections to the chip 3-terminal capacitor
The way a chip 3-terminal capacitor is typically used, you first cut the pattern of the line whose noise you want to reduce, such as the power line, insert the capacitor, and then connect the ground terminal (figure 3). Recently, a rather unconventional connection method has been proposed. This method is suitable when you want to stabilize voltage fluctuations in the IC by using a 3-terminal capacitor as a bypass capacitor for the IC power supply. This connection method is illustrated in Figure 4, where, unlike in Figure 3, the terminals are connected to the power supply line without cutting the power supply pattern. This connection method is called a "non-through connection" because the power supply line does not pass through the 3-terminal capacitor. Because the connection between the power supply line and capacitor is parallel, the impedance of this part is cut in half, the impedance of the bypass route is lowered, and voltage variation of the IC is reduced. In addition, as shown in the figure, by positioning the GND-side and power-side vias adjacent to one another, the magnetic fluxes generated by the current between them cancel each other, producing an apparent drop in the inductance of this part, further lowering the impedance. However, because some of the noise ends up passing through the power line without going through the 3-terminal capacitor, the effect of reducing the noise that escapes to the outside is significantly reduced compared to the conventional method of connection in which the 3-terminal capacitor is inserted after cutting the power line.
Written by: Yasuhiro Mitsuya, Product Promotion Dept., Component Business Unit, Murata Manufacturing Co., Ltd.
The information presented in this article was current as of the date of publication. Please note that it may differ from the latest information.