A Brief Introduction to PMbus®

28/02/2023

Power system developers increasingly deploy power management capability to optimize performance, uptime, and end-user experience for the complete range of any system powered by FEP PSU’s e.g.data, server, storage, industrial, and medical applications. Systems consist of a wide variety of devices, i.e.,
“targets”. Being able to control, configure, and monitor each device over a digital communication bus is required to achieve these objectives.

This bus needs to be easy to implement, and contain few lines, without compromising performance, as illustrated below.

Image of PMBus Physical Layer — Figure 1: PMBus Physical Layer

In addition to the physical layer, PMBus® provides a standard command language that defines addresses and registers promoting interoperability across many types of devices. The extensive command list, also provided, includes basic command functions as well as advanced and manufacturer-defined functions ensuring flexibility across many applications, e.g.:

Calibration
Data logging/Blackbox
FRU data
Cold Redundancy / Rapid On (example of this feature provided below)

Interoperability Promoted:

A wide variety of power devices and devices can be individually addressed and commanded by a single “controller” over PMBus®. For example:

Image of typical power system — Figure 2: typical power system

PMBus® Advantages:

Open standard protocol
Easy implementation
Flexible
Robust
Includes a purposefully defined command language
Control configure and monitor capability
Extensive and continuously improving
Royalty-free!

PMBus® Stewardship:

PMBus® is comprised of two elements, the physical interface, defined by SMBus, and the Command language & protocol defined by PMBus, both registered trademarks of System Management Interface Forum (SMIF, Inc.).

PMBus® Member companies from across a wide range of power and other industries maintain and improve upon the protocol. This pragmatic approach results in a highly interoperable, flexible standard. Murata is a contributing member of the PMBus® committee.

PMBus® Protocol Requirements

PMBus® is intended to optimize the performance and flexibility of a system and is not a product or device unto itself.
Some key rules explain the separation between the PMBus® Protocol and the individual power device operation:

Communication is controlled and initiated by the System/Host, and is known as the “controller”
The power devices targeted/addressed by the “Controller” are referred to as “target(s)”
Targets cannot communicate with each other
Targets must be able to:

power up safely and be unassisted by PMBus® communications
power up and operate without a power system manager/controller
support factory one-time, set-and-forget configuration and operate without PMBus® intervention after that point

Defaults from either non-volatile memory or pin programming

SMBus is compatible with I2C™ with advantages including:

More Robust (timeouts force bus reset)
More features such as:

SMBALERT# interrupt line
Packet Error Checking (PEC)

Low cost

PMBus® Specifications:

PMBus® is comprised of two parts:

Part One

Defines the basic Transport requirements, hardwired signals, and addressing

Numeric
Formats
Byte/Bit order
SMBus extensions
Bus speed
Electrical levels
Unpowered states
Block size
Addressing and resolution protocol (ARP)
Packet Error Checking (PEC)
Hardwired signals
Timing
Write protect
Accuracy
FW update

Part Two:

Defines the Command Language

Configuration
Data Format
Control
Status Monitoring
Fault Management
Setting and Monitoring output voltage and current
Information Storage, Inventory, user data, etc.
Calibration

PMBus® Interface Connections:

Image of Connections — Figure 3: Connections

Hardwired Signals:

Address

Each PMBus® Device/Target adapts a hardwired pin strapping address scheme, translated into a 7-bit address left shifted address byte. This unique address ensures “Controller” engagement occurs with the correct PMBus® Device/Target. Manufacturers adopt various address selection schemes (with trade-offs), such as:

a. QTY 3 address pins representing A0, A1, and A2: maximum address value choices, at the expense of space
b. Configurable high-order address bit(s) only: fewer address choices, reduced address lines, saves space
c. Single address pin, programable by resistor: fewer address choices, saves even more space

Optional PMBus® Hardware Signals:

PS_ON:

Provides On/Off control of main output in conjunction with PMBus® control/configuration commands.

SMBALERT#:

Provides real-time notice of a fault to supporting System/”Controller” by clearing immediately i.e., driven low, upon detection of a fault.

Because the system/”Controller” periodically reads the Target Devices STATUS registers (containing any set fault bit flags), this signal offers immediate notification and therefore, the maximum time for System/”Controller” to act.

PMBus® SCL and SDA Signals:

SDA and SCL are Open drain/collector signals that must be externally pulled up (3V/5.0V typically).

Image of Clock and Data Lines — Figure 4: Clock and Data Lines

PMBus® Command Language:

The System Management Forum best describes the command language as:

Extensive and comprehensive
Commands take effect immediately
Every value that can be written can be read
Not all devices support all commands. Devices will support the commands relevant to their application

Image of Very Basic Packet Structure — Figure 5: Very Basic Packet Structure

Image of Start/Stop/ACK Conditions — Figure 6: Start/Stop/ACK Conditions

Note: When the PMBus®/Target device fails to issue an ACK after a data frame, i.e., by pulling SDA to logic low, the “Controller” detects this as a NACK.

Byte and Bit Order:

The most significant byte is sent first. The least significant bit is sent first, within each byte.
Every Data frame (byte) is followed by an ACK (Acknowledged) or a NACK (Not Acknowledged when i.e., data not received correctly).
The “Controller”, upon detecting the NACK from the PMBus®/Target device, may issue a STOP condition to cancel communication or repeat the data.
The SDA bit is sampled by the PMBus®/Target device when the SCL transitions from low to high logic level and the “Controller” changes the state of the SDA line when the SCL transitions from logic high to logic low.
The “Controller” initiates the start of communications with a start condition, followed by the address of the PMBus®/Target device + a read or write bit to indicate the transaction type.
Upon recognizing its PMBus®/Target device address, the device sets an ACK condition and awaits further command.
When the “Controller” sets the bit “0” of the address byte to low, a write command is indicated. Completion of the write command is indicated to the “Controller” by the PMBus®/Target device issuing a NACK condition.

Command-List Organization:

The commands are defined within the Power Management Protocol Specification Part II – Command Language.

The command code range is from 0x00 through to 0xFF encompassing many standard, advanced, and manufacturer-defined application functions, Organized into categories:

Address
Memory, Communication, and Capability Related Commands
On, Off and Margin testing Related Commands
Output Voltage-Related Commands
Other Commands
Fault-Related Commands
Status Commands
Parametric Reading
Manufacturer’s Information
Manufacturer’s Ratings

PMBus® Defines an interoperable, easy-to-implement bus and command protocol enabling designers with configuration, control, and monitor capability.

Advanced PMBus® Function Example, “Cold Redundancy”

Conventional Vs Cold Redundancy:

Conventional redundancy is ubiquitous in power system deployments. It occurs when the total load current is shared by a fixed quantity of power supplies 100% of the time.

Cold Redundancy is a sharing mode established using PMBus® commands made by the system/“Controller”. Load-sharing flexibility and optimization possibilities are the aim of this feature. For example, during off-peak periods, as few as one power module sources 100% required system load current. This shifts the active power supply’s operating point efficiency closer to the green area, above, as other power supplies are shed.

Basic Concept:

The System/Controller sets each of the redundant power supplies to one of these load-sharing states:

Active State: “participates” in equal sharing of the overall system load
Cold Standby State: No load-sharing participation

The System/“Controller“ can utilize either of these sharing mode controls:

Command the on/off status of each power supply
Commanding the redundant power supplies to autonomously manage the load-sharing state, individually. ISHARE signal is compared with preset, staggered threshold limits, in the order set by the “Controller” mapping each power supply to a unique index identifier.

Rapid_ON Hardware signal:

This signal must be interconnected to participating power supplies. It is used to force all power supplies to turn on rapidly when a fault is detected, without compromising system operation.
Power supply modules not actively delivering load must meet these criteria:

Turn off the output at ORing MOSFET
Energize the output capacitor(s) periodically to minimize any glitches
Force output on with 100us of the CR / Rapid_On bus changing to a “High” state

Several Murata Front End Power and DC/DC Products support PMBus®.

Conclusion:

Developing reliable power systems optimized for performance requires advanced digital control and interconnection of the connected components. PMBus® provides a physical interface layer and command language, making power management easy to implement. The system controller can digitally command target addressable devices over PMBus® to perform an array of tasks.

Murata features PMBus® capability across many products including Front-End Power, Isolated and non-isolated Board-Mount Power, and DC-DC POL converters.